1. Field of the Invention
The present invention relates to a soft-output decoder for controlled intersymbol interference channels, and more particularly to an apparatus and a method for reducing complexity in a soft output Viterbi decoding algorithm used in partial response channels, such as those used to model magnetic recording channels.
2. Description of the Related Art
Transmission of digital data is inherently prone to interference that may introduce errors into the transmitted data. Error detection schemes have been suggested to determine as reliably as possible whether errors have been introduced into the transmitted data. One such scheme is known as convolutional coding.
Convolutional codes have been introduced to allow receivers of digital data to correctly determine the transmitted data even when errors may have occurred during A transmission. The convolutional codes introduce redundancy into the transmitted data and pack the transmitted data into packets in which the value of each bit is dependent upon earlier bits in the sequence. Thus, when a few errors occur, the receiver can still deduce the original data by tracing back possible sequences in the received data.
Optimal decoding is often a very complex task, and may require large periods of time, which are not usually available. In order to overcome this problem, iterative decoding techniques have been developed. Rather than determining immediately whether a received bit is a zero or a one, the receiver assigns each bit a value on a multi-level scale representative of the probability that the bit is a one. A common scale is the logarithmic likelihood ratio (LLR). The LLR represents each bit by some integer in an interval such as, for example, {−32,31 }. In this example, the value of 31 signifies that the transmitted bit was a one with very high probability, and the value of −32 signifies that the transmitted bit was a zero with very high probability, whereas the value of 0 indicates indeterminacy as to whether the transmitted bit was a zero or a one.
Data represented on the multi-level scale is referred to as “soft data”. Iterative decoding is usually soft-input/soft-output; i.e., the decoding process receives a sequence of inputs corresponding to probabilities for the bit values and provides as output corrected probabilities which take into account the constraints of the code. Generally, a decoder which performs iterative decoding uses soft data from former iterations to decode the soft data read by the receiver. The iterative decoding is carried out for a plurality of iterations until it is believed that the soft data closely represents the transmitted data.
Decoding techniques for convolutional codes are very well known in the literature at and are the subject of many patents. For example, see U.S. Pat. Nos. 6,182,261; 6,161,209; and 6,145,114, the contents of each of which are incorporated herein by reference. In addition, several commonly assigned copending patent applications relate to this subject matter. These include U.S. patent application Ser. No.09/730,597, filed on Dec. 7, 2000, and entitled “Address Generator for IDPC Encoder and Detector and Method Thereof”; U.S. patent application Ser. No. 09/730,752, filed on Dec. 7, 2000, and entitled “LDPC Encoder and Method Thereof”; U.S. patent application Ser. No. 09/730,603, filed on Dec. 7, 2000, and entitled “LDPC Detector and Method Thereof”; and U.S. patent application No. 09/730,598, filed on Dec. 7, 2000, and entitled “Parity Check Matrix and Method of Forming Thereof”, the contents of all of which are incorporated herein by reference.
Reference is now made to FIG. 6, which is a block diagram of a data transmission system as described in more detail in commonly assigned copending application “Address Generator for IDPC Encoder and Decoder and Method Thereof”, filed on Dec. 7, 2000 and assigned application Ser. No. 09/730,957, the contents of which are incorporated herein by reference. In general as shown therein, a digital data transmission system comprises a transmitting section 300′ for transmitting user data to receiver 500′ via communication channel 401.
The operation of transmission section 300′ will now be explained. Prior to processing by transmitting section 300′, input or user data maybe encoded with an error correcting code, such as the Reed/Solomon code, or run length limited encoded (RLL) or a combination thereof by encoder 302. Addresses for the parity equations of linear block code encoder 304 are generated by address generator 328 in accordance with an index of the bits of data, the index being determined by address generator 328. Address generator 328 is responsive to counter 730 under the control of controller 740. Controller 740 synchronizes counter 730 to the output of encoder 302 so that counter 730 can provide a count of the number of bits in a codeword output by encoder 302 and a count of the number of codewords.
Linear block code encoder 304 utilizes the user data and address from address generator 328 to provide the parity bits to multiplexer 306. Linear block code encoder 304 is preferably implemented as a low-density parity-check code (LDPC) encoder as described in commonly assigned, copending patent application entitled “LDPC Encoder and Method Thereof”, filed on Dec. 7, 2000 and assigned application Ser. No. 09/730,752, the contents of which are incorporated herein by reference. The parity data from linear block code encoder 304 is combined with the data encoded by encoder 302 by multiplexer 306 for input to channel transmitter 310. Preferrably, the combined data consists of series of a pair parity bits followed by 40 bits of user data. This constraint is established by encoder 302.
Transmitter 310 transmits the combined user and parity data from multiplexer 306 typically as an analog signal over communication channel 401 in the channel domain. Communication channel 401 may include any wireless, wire, optical, magnetic and the like.
Receiver 500′ comprises an analog to digital converter 502 to convert the data transmitted on communication channel 401 to a digital signal. The digital signal is input to soft channel decoder 504, which provides soft or probabilistic information of the detected data to soft linear block decoder 506. Soft channel decoder may be implemented as a Soft Viterbi Detector or the like, and address generator 530 may be constructed similarly as address generator 328 in transmission section 300′. The soft information output by soft channel decoder 504 remains in the channel domain and is decoded by soft linear block code decoder 506, in accordance with the address of the parity equations generated by address generator 530. Address generator 530 is responsive to counter 735 under the control of controller 745. Controller 745 synchronizes counter 735 to the output of soft channel decoder 504 so that counter 830 can provide a count of the number of bits in a codeword output by soft channel decoder 504 and a count of the number of codewords.
Soft linear block code decoder 506 operates in combination with soft channel decoder 504 and address generator 530 in an iterative fashion. Soft linear block code decoder is preferably implemented as a low-density parity- check code (LDPC) decoder as described in commonly assigned, copending patent application entitled “LDPC Decoder and Method Thereof”, filed on Dec. 7, 2000 and assigned application Ser. No. 09/730,603, the contents of which are incorporated herein by reference.
After the iterative process has completed, the output of soft linear block code decoder 506 is passed on for further processing to decoder 508. Decoder 508 is implemented to perform the reverse operations of encoder 302 or correct for any data errors.
One type of communication channel for which soft-output decoding of convolutionally encoded data is often employed is the controlled intersymbol interference (ISI) channel. One special class of controlled ISI channels that is commonly used is that of the partial response (PR) channels, which are used to model magnetic recording channels. Because of the redundancy inherent in a convolutional code and the iterative nature of the decoding process, the decoding method used may be highly complex, and therefore consume an unacceptably high level of computing resources. Accordingly, there is a need for a new soft-output decoding method having reduced complexity while continuing to yield low bit error rates for PR channels.